Difference between address width, addressability and word size.

[u/Junior-Title-1987]

I’ve been reading through a computer systems book to become a more knowledgable programmer and I’m not fully understanding the difference between the concepts of address width, addressability and word size. This is how I currently understand them:

Address width refers to the size of pointer data — that is, the value of the pointer. The address width determines how many possible addresses are capable of representation and thus, is one factor in determining the total size of addressable memory.

Addressability refers to the size of data stored at a given address.

Word size refers to the “natural” unit of instruction of the processor. Conventionally, most CPU registers have a width that corresponds with the address width so that a full pointer fits inside a single register. This simplifies the set of operations necessary for the CPU to understand.

I think the connection between address width and word size is what I’m most confused about. For example, if the address width was 2x the word size, would that mean that the CPU would need a combined “read+move” instruction to fully process a single pointer?

[u/wrosecrans]

if the address width was 2x the word size, would that mean that the CPU would need a combined “read+move” instruction to fully process a single pointer?

The 6502 is a good example to study. It is mainly called an 8-bit CPU. But it had a 16 bit address bus. So you couldn't really load a full pointer into one of the normal-ish 8-bit registers A, X, and Y. You needed to hard code memory addresses, or jump relative to an address stored in memory.

https://6502.org/users/obelisk/6502/addressing.html

https://6502.org/users/obelisk/6502/registers.html

The classic 16 bit real mode of x86 is also informative - it uses two 16 bit registers for memory accesses on a 20 bit address space. Using segmented memory, all operations were done with 16 bit pointers that fit in a register, relative to a mapped memory segment within the bigger 20 bit address space.

[u/pgetreuer]

Addressability refers to the size of data stored at a given address.

AIUI "addressability" refers to whether a given unit of memory has an address. For instance, memory bits are not individually addressable on x86 (but the containing byte is). Or memory beyond 4GB is not addressable by 32-bit pointers.

Conventionally, most CPU registers have a width that corresponds with the address width so that a full pointer fits inside a single register. I think the connection between address width and word size is what I’m most confused about. For example, if the address width was 2x the word size, would that mean that the CPU would need a combined “read+move” instruction to fully process a single pointer?

What you say sounds reasonable in the ideal, but it is complicated in practice. Some ISAs have registers of different sizes, e.g. the 80386 and later x86 has eax, ax, and al respectively of sizes 32, 16, and 8 bits. This makes it murky to say what the "natural" data unit size is. It's also possible in some ISAs to use a pair of registers together to make a pointer, e.g. on 80286 with a "segment" plus an "offset" to address up to 1MB with 16-bit registers. Apologies for the less than clear answer, I hope that's some help!

[u/Syresiv]

For example, if the address width was 2x the word size

In that case, you'd have to architect the CPU around the constraint that you can't refer to any arbitrary address in a single instruction.

That combined read+move isn't necessarily the only solution, but it is a solution. You could also have an address space register that stores the upper half of the address, or read an address from two registers instead of one.

[u/high_throughput]

For example, if the address width was 2x the word size, would that mean that the CPU would need a combined “read+move” instruction to fully process a single pointer?

Not sure what you mean by "read+move". The 8086 had 16-bit registers but 20-bit addresses, so two registers were combined implicitly or explicitly. 

For example mov ax, cs:[bx] would combine the csregister with bx explicitly, while mov ax, [bx] would implicitly use ds

[u/flatfinger]

Typically, "addressability" refers to the ability to write a chunk of data without affecting adjacent data. A system can easily allow individual octets to be read from RAM the memory subsystem is incapable of accessing anything smaller than 64-bit chunks, by simply having the CPU perform a 64-bit read and only look at 8 bits of the result. Nothing special would be required to support concurrent reads. If one core reads a 64-bit word for the purposes of inspecting an 8-bit piece of it, and another reads that same 64-bit word for the purposes of inspecting a different 8-bit pieces, neither of those accesses will interact with the other in any way.

Writes to memory are a different story. If a program wants to write an 8-bit chunk and memory only supports 64-bit accesses, a system would need to read 64 bits, modify 8 bits of the copy that was just read, and then write all 64 bits back. If two cores try to simultaneously update different 8-bit portions of the same 64-bit word, a lot of arbitration would be needed to ensure that both 8-bit chunks get updated without disturbing anything else. If, however, the system had octet-addressable storage, then the system would record the fact that each thread had only written to one particular 8-bit portion of the 64-bit word, and refrain from writing back to RAM data which had been read but not modified.