struggling with vhdl timing issues

[u/Travis-Jenkins]

hey folks, Im currently working on a VHDL project for one of my classes and Ive hit a bit of a wall. The design is a simple state machine, but Im having issues with timing.

Ive tried simulatting it with ModelSim and it looks fine there, but once I implement it on the FPGA, the timing seems off. The outputs aren't changing as expected and Im suspecting it might be a clock issue.

Im using a Xilinx Spartan 6 board and the clock is set at 50MHz. Ive tried adding some timing constraints in the Xilinx ISE, but Im not sure if Im doing it right. Any tips on what to look for or adjust? Im kind of new to this and feeling a bit lost.

[u/SandwichRising]

You need to assign a 20ns period to your main clock with timing constraints and then see if it passes with a timing report. Google says Xilinx uses .xdc files for this and that you need to 1) Use the Constraints Wizard: Run the Vivado Constraints Wizard on a synthesized design to auto-detect missing primary clocks and basic I/O delay setups. And then 2) Check Timing Reports: Run report_timing_summary after implementation to view worst negative slack (WNS) and find critical performance bottlenecks.

Hopefully that process works for you, but if it doesn't the flow is the same: 1. Define constraints, 2. Check timing reports. You want your slack to be positive, a negative slack number means your design runs out of time before the next clock.