r/haskell 1d ago

Functional Programming on FPGA: How Clash Works | QBayLogic

https://qbaylogic.com/blog/functional-programming-on-fpga/
52 Upvotes

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u/Blueglyph 1d ago

I can see why a functional language is more straightforward and safer at specifying data paths than an imperative language (though abstraction is what compilers are for), but how are you modelling time?

High-level synthesis had promised huge gains in productivity, and it's indeed quicker for simulating simple data-focus modules, but the paradigm has completely failed in practice because of its inability to handle control logic and the difficulty to reach timing closure—not to mention the increased resources, but that could have been solved in the future with better HLS-synthesis co-optimizations, I suppose.

I don't see how Haskell would differ from C in that regard.

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u/pr06lefs 21h ago

According to the docs this isn't 'high level synthesis' in the sense of translating a block of C style logic into a verilog implementation that is structurally quite different. This is more of a one-to-one correspondence between the haskell functions and the generated verilog.

2

u/callbyneed 19h ago

but how are you modelling time?

Using the Signal abstraction: https://clash-lang.org/blog/2025-02-07-signals/. The basic idea is that you can write:

counter = register clock 0 (counter + 1)

and evaluate it to a list of:

[0, 1, 2, .....

because lazy evaluation first resolves the start-up value you pass in (0), applies +1 to it to compute the second item in the list, and so forth.

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u/Blueglyph 17h ago

Thanks for the link!

Yes, I see the idea, now.