r/FPGA Jul 18 '21

List of useful links for beginners and veterans

1.1k Upvotes

I made a list of blogs I've found useful in the past.

Feel free to list more in the comments!

Nandland

  • Great for beginners and refreshing concepts
  • Has information on both VHDL and Verilog

Hdlbits

  • Best place to start practicing Verilog and understanding the basics

Vhdlwhiz

  • If nandland doesn’t have any answer to a VHDL questions, vhdlwhiz probably has the answer

Asic World

  • Great Verilog reference both in terms of design and verification

Zipcpu

  • Has good training material on formal verification methodology
  • Posts are typically DSP or Formal Verification related

thedatabus

  • Covers Machine Learning, HLS, and couple cocotb posts
  • New-ish blogged compared to others, so not as many posts

Makerchip

  • Great web IDE, focuses on teaching TL-Verilog

Controlpaths

  • Covers topics related to FPGAs and DSP(FIR & IIR filters)

r/FPGA 2h ago

VCD Viewer

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9 Upvotes

Last week I decided to continue one of my ongoing side projects: A VCD viewer directly in the terminal.

Mostly because I was fed up with the strange UX/UI of traditional tools like QuestaSim or GTKWave. Im not saying my "fuck this shit, im doing it myself" approach resulted in something actually better, but it does look quite cool in my opinion.

Its available here, but keep in mind that it only works with Linux and does not support all VCD features.


r/FPGA 2h ago

Am I completely limiting my career opportunities by avoiding defence companies (UK)?

5 Upvotes

Background: I have a Master's in EEE from a Russell Group university.

I'm looking for graduate/entry-level FPGA jobs but trying to completely avoid defense companies. I know this is a topic of debate, but that's not the reason for my post.

I want to know: if I'm not keen on working in the defence industry, am I limiting myself to a point where it's better to change career paths because of how hard it is to find an entry-level FPGA job elsewhere?


r/FPGA 10h ago

First Fpga

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20 Upvotes

Is it a good combo to start with an FPGA? The price is very attractive, it supports PetaLinux, and is programmable from Vivado.


r/FPGA 16h ago

Need help regarding a self-learning project

19 Upvotes

Hi all, I am an FPGA engineer but in my current organisation doing some other work which is not at all based around FPGAs, so i am scared that i might start forgetting concepts, so to keep myself learned and stick to FPGAs i am thinking of starting a new project (which has to be complex). So I am looking for project ideasand also is there any online resource where i can check (virtually) that my project is working on the FPGA.
Need help!


r/FPGA 13h ago

Advice / Help Prerequisite background/knowledge to start working on FPGAs

9 Upvotes

I have a relatively basic understanding of electronics. I plan to take this further during my gap year before I start university (EEE), deferred entry so I can put more time into learning. I have a few questions:

-What do I need to cover before starting a project with a FPGA?
-What maths and physics topics are needed to form a solid foundation? (I've completed my A-levels, up to calculus 1 in the states iirc)
-Are there any recommended books or resources (already took a look at the beginner's post but wanted to know if there's more)?
-How do I set myself up well for starting a degree in electronics engineering?

Interested in RF and Communications, anything in that sort of area, also had a look at signal processing and thought that was cool which lead me here. If anyone could give me project ideas to build up some experience in these areas and if there's any software/programming languages worth learning that would be greatly appreciated.


r/FPGA 2h ago

Intersection between LLM optimisation and hardware

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1 Upvotes

r/FPGA 5h ago

Looking for Referral

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1 Upvotes

r/FPGA 19h ago

Advice / Solved How good is this FPGA project

10 Upvotes

How good is it, and any tips/ways I can make this project even better/more impressive?

Idea is: market-data-style packets come into the FPGA, the RTL parses the packet, extracts fields like symbol, bid/ask price, size, sequence number, and timestamp, updates simple book/top-of-book state, runs fixed-point decision logic, checks a hardware risk gate, and outputs a simulated order/cancel message.

10GbE/UDP packet input

-> SystemVerilog parser/decoder

-> book state

-> fixed-point decision logic

-> hardware risk checks

-> order output

-> latency counters

Software side:

Python/cocotb for packet generation, randomized verification, and golden-model checking

C++ for packet replay, control/configuration, logging, and simulated exchange output


r/FPGA 1d ago

Career Advice: Masters or Work?

16 Upvotes

Hey everyone,

I'm going into my 6th and final year of Electrical Eng. in Canada (Did 3 years in Eng Physics, switched to pure EE w/ minor in Phys during my 1yr co-op). I switched programs mainly to get more electronics courses as my old program had pretty limited Elec electives, and poor career prospects.

I got interested in digital hardware design (mainly FPGA) from my Capstone project (FPGA based Extended Kalman Filter for radar) and a summer research project (PQC HW acceleration), and want to pursue it as my career. I've been approached/recommend to take a Masters by a few profs, but am unsure if it will be beneficial or just delay me from starting to work. I have a pretty high CGPA (11.30/12) so I definitely could get in if I wanted too, and could get scholarships to cover most of the costs.

So I see two options,

  1. Start work right away. Pros: make money, less school, 2 year headstart on my career. Cons: could be limiting my career potential, would likely never go back to school.

  2. Do my Masters. Pros: get a bit more time to decide on a future career, have a higher level degree, possibly open new career paths, would likely get scholarships to pay for most of it. Cons: Delay career by 18-24 months, Masters experience might not translate to industry experience.

How useful is a masters in digital hardware design (FPGA/ASIC)? For anyone that got their masters, did it help?

Thank you in advance for any advice!


r/FPGA 16h ago

Searching for mentorship/co founder

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0 Upvotes

QaviCoreX is a custom RISC-V processor we're building for AI acceleration. We're implementing custom AI instructions directly in hardware and targeting FPGA deployment. We've moved beyond the idea stage into actual Chisel/Chipyard hardware prototyping, and we're currently working on scaling the design because our current FPGA is running out of resources.

The idea is to move AI operations closer to the processor itself instead of relying entirely on software. We're experimenting with custom hardware instructions such as multiply-accumulate and activation operations, so AI workloads can potentially execute much more efficiently.

Our current implementation is resource-limited on the 100T device. The dominant constraint is LUT utilization, and based on our synthesis results, moving to a higher-capacity device gives us the headroom needed for the complete architecture. We're also investigating optimization and architectural changes rather than simply scaling the FPGA.

Want more details go to my blog https://qavicorex.blogspot.com/p/home-page.html


r/FPGA 1d ago

AI in FPGA Design

5 Upvotes

Hello everyone

Do you use artificial intelligence in your work? Have you deployed local models on your servers? If so, what are the purposes of such a model?

I already have experience as a programmer, and I am currently gathering information about what areas of work can be covered by a local model with access to the project and the board.


r/FPGA 2d ago

Xilinx Related Help Finding Files for Vivado

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55 Upvotes

Hi everyone,

I recently bought this Zynq 7020 Development board. Dont hate, i know its not perfect, but it has everything i wanted.

The biggest problem is that i dont have the Constraint files and the seller is currently ghosting me.
Here is what I managed to identify from the silkscreen and the chips:

  • Manufacturer: Bo Chen Jing Xin (博宸精芯)
  • Model: ZYNQ MINI 开发板 (RevB / 20221015)
  • FPGA: XC7Z020
  • RAM: Micron MT41K256M16TW-107 (512MB DDR3L)
  • Flash: 128Mbit QSPI (25QS128FVSG)
  • Peripherals: Dual Gigabit LAN (1x PS, 1x PL), Dual SD Card (1x PS, 1x PL), 0.96" I2C OLED display.

Does anyone happen to have a Baidu Pan link, Github repo or even a zip file with schematics and the Vivado preset/XDC files for this specific board?

I have attached a picture of the front and back view (The back has a pinout for the EXT IO header, but obviously lacks the info for the built-in peripherals).

Any help or Pointers to a complete board file would be appreciated!

Edit:
I got a response from a nother seller i contacted and actualy got the files.

I checked the silk screen on the back and they matched.

If anyone else needs theses files this is the link

Edit 2: I just finished reworking the Constraint files since they were in a bad shape and didnt allways match the Circuit Diagram. Still working on renaming the files.

You can find all the resources here in google drive.

Also pain in the ass to download...


r/FPGA 1d ago

Xilinx Related Vitis Annoyance

6 Upvotes

Does anyone know how to disable this 'Activating Git Base (built-in)' message that comes up in Vitis? It never goes away and seems to really slow down Vitis, whcih sometimes doesn't allow me to build/run. This forces me to close Vitis, reopen and hope it doesn't appear again. I have already unchecked 'enable git' in settings.


r/FPGA 1d ago

First working on icebreaker

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3 Upvotes

Just Started with real bd


r/FPGA 2d ago

BASYS2

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94 Upvotes

I found my old board BASYS2 is still working now.


r/FPGA 2d ago

Advice / Help 720p hdmi from gowin primer 20k gives white image on xreal googles. Run out of ideas

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13 Upvotes

So I am trying to make a analog using a gowin primer 20k so far it kinda works but I am getting stuck past trying to interface the xreal googles. I tried with my pc set to 720p and that works flawlessly but whenever I tried with the fpga it just never worked. It seems that whatever is the first lane is getting copy pasted top to bottom. I thought maybe there was a bug on the dvi tx from gowin so I tried this project changed the target, changed the pins and regenerated the rpll to my board. Flashed it and the same symptoms. I am kinda a bit lots what to try. Bought another hdmi to usb c converted in the meantime just to try it out maybe but while I wait for that to arrive does anyone have any clue what could be wrong? I knew the googles are a bit of a hard to please target idk at this point. I found this discussion about similar troubles with a eevblog and there am I a bit lost if that applies to the tang primer 20k


r/FPGA 2d ago

Interview / Job Optiver OA for FPGA Internship Advice

1 Upvotes

Hi guys. I've never really done an OA before since I've been more focused on research and projects and was wondering how difficult the OA is for Optiver FPGA internship? I'm just wondering what topics they'll cover, if they're all like single digit number of lines kinda length or if some get a little lengthier. Are we expected to know Networking concepts in the OA or is that saved for the video call interviews? Thanks for any help!


r/FPGA 2d ago

Advice / Help Tuxedo Computers for Vivado

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5 Upvotes

Has anyone had any experience running Vivado on a Tuxedo Computer ( Tuxedo Infinitybook Max 16). My default choice was to go for a thinkpad P14. I am attaching the specs of both the devices. the tuxedo is costing me less. i will mostly be running vivado and maybe cadence virtuoso.


r/FPGA 2d ago

Has anyone finished the oscilloscope project from Jim Ledin's FPGA book?

53 Upvotes

I spent the past ~8 months building the board and the code up to a working prototype (as described in his book here), but then in Chapter 9 he decides to hit you with the ultimate blue ball:

https://imgur.com/a/osebTOU

I messaged him to see if he had the code that actually implements reading data from the FIFO and writing it to the appropriate addresses in DDR3, but wanted to see if anyone's actually successfully worked it out before.

I've spent probably over $1k in EE lab equipment and over half a dozen digikey/oshpark orders taking it this far. I have to see it through lol

edit: what I do have so far is here - https://codeberg.org/rhedogian/arty_a7_oscope


r/FPGA 2d ago

Wavekit: cycle-centered waveform analysis in Python

9 Upvotes

Most waveform tools and workflows are organized around signal changes over time, while many hardware questions are really about cycles and the events that span them. Engineers still end up tracing signals through the waveform, placing cursors, and counting cycles by hand as part of the analysis.

AI-assisted workflows haven't automatically eliminated this gap either. The signal changes still have to be reconstructed into higher-level behavior before anyone, human or model, can reason about what happened. That reconstruction happens implicitly, leaving nothing to review or reuse.

Wavekit is a Python library for digital waveform analysis that treats clock cycles as first-class citizens. With wavekit, signals are sampled on clock edges and can be operated on like ordinary Python values.

For example, one common design question is whether a FIFO is deep enough. A waveform viewer can show that the FIFO gets full, but checking its occupancy over a long simulation still takes manual work. With wavekit, the same check is a few lines of Python:

import numpy as np
from wavekit import VcdReader

with VcdReader('fifo_trace.vcd') as reader:
    w_ptr = reader.load_waveform('tb.fifo.w_ptr', clock='tb.clk')
    r_ptr = reader.load_waveform('tb.fifo.r_ptr', clock='tb.clk')

    depth = 16
    occupancy = (w_ptr + depth - r_ptr) % depth
    util = occupancy / depth

    # Waveform is backed by NumPy, so np functions work directly on .value
    print('average utilization:', np.mean(util.value))
    print('maximum utilization:', np.max(util.value))
    print('p95 utilization:', np.percentile(util.value, 95))

Behavior spanning multiple cycles can be described with Pattern. For example, an AXI-Lite read transaction starts with an AR handshake and finishes with an R handshake:

import numpy as np
from wavekit import VcdReader
from wavekit.pattern import Pattern, match

with VcdReader('axi_lite_trace.vcd') as reader:
    # eval() loads signals and evaluates the expression in one call
    request = reader.eval('tb.arvalid & tb.arready', clock='tb.clk')
    response = reader.eval('tb.rvalid & tb.rready', clock='tb.clk')

    result = match(
        Pattern()
        .wait(request)
        .consume(response)
    )
    latency = result.end.clock - result.start.clock

    print('average read latency:', np.mean(latency))
    print('maximum read latency:', np.max(latency))
    print('p95 read latency:', np.percentile(latency, 95))

Wavekit stays focused on waveform operations and primitives for matching multi-cycle behavior. Everything else stays in ordinary Python, so NumPy, pandas, and other Python libraries remain available for statistics and design-specific processing.

Wavekit does not assume a particular protocol or workflow — the primitives above can be combined to build the analyses your own design needs. The repository also includes more involved examples, including AXI transaction extraction and DMA command analysis.

The project is open source and available on PyPI:

pip install wavekit

[GitHub repository][Documentation]

Happy to answer questions in the comments.


r/FPGA 1d ago

FPGA Job Helppppppppppppp!!!!!!!!!!!!!!!!!!!!

0 Upvotes

is there any chance in Pakistan to get a good high paying job in fpga remotely?


r/FPGA 3d ago

It was years in the making

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38 Upvotes

r/FPGA 2d ago

Hands on EXP with Tang FPGA Studio

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0 Upvotes

If you’ve ever messed around with the cheap Sipeed Tang Nano or Tang Primer series (like the 9K or 20K), you already know the drill. The hardware is incredibly cheap and powerful, but the vendor software stack and fragmented open-source toolchain setup can be a massive headache to piece together.
I recently downloaded Tang FPGA Studio to see if it could clean up my workflow, and after running a few test projects through it, I wanted to share my thoughts. It is a community-driven, open-source IDE, and the UI/UX changes the entire onboarding experience.

What went right during my test run:

First off, it completely bypasses the typical first hour frustration. Usually, you have to manually hunt down Yosys, Nextpnr, and configure openFPGALoader just to get JTAG communication working. This app bundles the toolchain into a single installer, meaning I went from a clean install to flashing code without having to fight my system's environment variables.

The project wizard is another huge quality of life upgrade. It explicitly filters your project templates by your exact board model. If you have ever accidentally compiled a design using a Dock pinout for a bare Nano board and spent an hour debugging why your hardware was silently dead, this completely solves that pain point.

The actual day to day workspace feels cohesive. It brings your Verilog editor, linter, simulation tools, and waveform viewer into a single modern interface. It honestly feels more like working in a polished code editor or a modern microcontroller IDE rather than fighting a clunky, bloated vendor tool from the early 2000s. Iterating on code and pushing it to SRAM is incredibly fast.

I suggest you guys try it out beginners may find it helpful - Tang FPGA Studio on GitHub


r/FPGA 2d ago

Is an ITCH parser an internship worthy project

0 Upvotes

For context, I am going my 3rd year of Computer Science degree, but got very interested in FPGAs over the last summer. Currently going through the ZipCPU lectures, and some theory from the Harris&Harris book.

Located in Canada, I think I would like to pursue FPGAs as a career after my Bachelors, looking into it, it seems as though an internship is pretty required to for that unless you get MSc or smth. So my idea for a major project is an ITCH parser, that accepts a bytestream, parses it, and then outputs relevant stats via AXI-lite, all backed by formal verification, running on Arty A7-100T.

I simply wish to know if that's a good idea or not.