Senior ASIC Verification Engineer

I am hiring for both ASIC Design and Verification Engineers - both Mid and Senior levels. These are all full time, direct hires with Cornelis Networks. Good salary and benefits with Series B Equity. Please email ( [scott.kwait@cornelisnetworks.com](mailto:scott.kwait@cornelisnetworks.com) ) me directly for consideration, direct applicants only (no agencies or 3rd parties). Apply directly using this link for the US, or this link for Costa Rica.

Job Description

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. 

Cornelis Networks is hiring a Senior ASIC Verification Engineer with advanced skills and knowledge in key areas required to verify world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. As a member of the ASIC leadership team with hands-on technical experience, you will be responsible for the verification closure of entire projects, including design modules, sub-systems, and SoCs. You will drive a wide range of activities including test-planning, UVM based testbench development, regression and coverage closure. You will have the opportunity to partner and collaborate with ASIC design, emulation, system hardware and post-silicon teams and help create a first-pass silicon success. A preferred candidate will have 8+ years of relevant experience in networking hardware verification, proven expertise in verifying one or more of the following: 50G, 100G, 400G Ethernet MAC/PCS protocols, UDP, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking. Experience utilizing AI tools to generate test plans and improve the productivity of verification process and team is highly desirable.

 Key Technical Responsibilities:

• Define overall SOC level verification strategy, technical planning, direction
• Enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels
• Develop and execute functional tests according to verification test plans
• Instrument TB for functional and code coverage and drive to closure based on the coverage metrics
• Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality

Team Responsibilities: 

• Day-to-day guidance and leadership of team members
• Driving results via mentoring, coaching, and counseling
• Education of team in the use of AI tools to enhance productivity and efficiencies
• Generation and enforcement of coding and verification guidelines

Minimum Qualifications: 

• 8+ years of experience with the following:
• Hands-on experience with writing code using UVM/System Verilog
• Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools
• Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
• Experience in ground up testbench development
• Experience with revision control systems like Git or SVN etc.
• B.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering

Preferred Qualifications: 

• M.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
• 8+ years of relevant experience in networking hardware verification, proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking
• One or more scripting languages (TCL, Python, Perl, Shell-scripting)
• Track record of first-pass success in ASIC and Systems

Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.  

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. 

In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. 

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. 

I'm 19, first year Electrical and Electronics Engineering in Turkey. I'm interested in computer architecture. I research on memory systems and DRAM security, I'm in a computer architecture lab at my university. The plan was a PhD abroad and then working somewhere that designs its own chips.

I've started doubting that plan and I want to hear from people who actually work in the field.

1. Placement and floorplanning seem mostly automated now (AlphaChip, Cerebrus, DSO.ai), and LLM generated RTL keeps improving. If you work in RTL, verification or architecture, has your actual day to day changed much in the last two years? Are teams hiring fewer juniors?
2. Is it true that architecture, spec and verification are the hardest parts to automate and physical design is the easiest? Or is that just what people want to believe?
3. Is it getting harder for new grads to get into hardware, like it clearly has in software? Is the engineer shortage everyone talks about real from the inside?
4. What actually counts for a hardware job or a PhD application? A working and verified core on an FPGA? Open source silicon contributions? Papers? I have 2-3 years and I want to spend them on the right thing.
5. I'm a Turkish citizen. How much do visas and export control/clearance rules actually block you in this field? Is Europe easier than the US for hardware?
6. How does pay grow for a hardware engineer over 10-15 years compared to software? Not exact numbers, just the shape of it.

Why I'm asking all this: here medicine is the default safe high income path, my exam score was good enough for it and I picked engineering instead. I'm reconsidering, and I'd rather decide based on real information. Honest answers are fine, I don't need to be encouraged.

Thanks.

Hello everyone,

I am an electronics and electrical communication engineering fresh grade and I have a very bad GPA 2/4

but I have taped out an edge ai chip for my graduation project and it was sponsored by a small design house on some old node and fortunately this chip went commercial. I also have 2 ieee publications ( the 2 papers are related to my graduation project). I need to apply to a master at one of top tier universities specially in Europe to make up the bad bachelor records but I think I won't be accepted due to this GPA. any recommendations or advices ?

It doesn't have to be sponsored, I can self fund my master

Hey everyone,

I’m currently pursuing my M.Tech and aiming to build a career in Physical Design.

So far, my hands-on exposure includes:

• Custom IC / Analog Design: CMOS circuit design and physical layout in Cadence Virtuoso, along with manual layout optimization (DRC/LVS/PEX).
• RTL-to-GDSII Implementation: Full digital implementation flow using both commercial suites (Cadence Innovus/Genus) and open-source EDA tools (OpenLane/OpenROAD).
• Synthesis & Timing Exploration: Experimented with dynamic frequency scaling during synthesis to analyze its impact on power, area, and timing metrics (WNS/TNS).

I want to take my practical understanding to the next level and work on something that closely mimics real-world industry challenges rather than just running a standard flow on a toy block.

For the PD engineers here:

1. What specific project would you recommend I work on next?
2. Which open-source blocks/macros or benchmark suites (like RISC-V cores, OpenPOWER, or complex DSP blocks) are best suited for demonstrating solid PD skills?
3. What specific tapeout-ready skills or edge cases do hiring managers look for on a fresh grad’s resume that set them apart?

Any feedback, project ideas, or resources would be greatly appreciated! Thanks in advance.

I am an analog designer working in memory phy ( ddr/lpddr/ gddr). Mostly in the receiver design. Getting a very lucrative offer but the team does IO designs ( GPIO, LVDS, I2C, I3C etc) and POR circuits. Should I jump the ship?

Given I have 7 yoe currently. I am thinking to chose new company and stay for 2-3 years and then move back to high speed. This compensation is extremely good that what’s making my mind swing.

Please guide what are pros and cons?

Final year ECE student. I’m doing an internship at a semiconductor company right now with the DV team, and they’ve offered to host my final year project. The title they proposed is about using LLMs for design verification.
I’m targeting front-end ASIC roles after graduation DV and RTL design, I’m open to either. So my concern is this: will a project like this actually give me a solid understanding of verification UVM, coverage, assertions, debugand. And enough design-side depth to be credible for RTL roles too or will I spend the whole year on prompting, scripting, and pipeline plumbing and come out knowing more about LLMs that about hardware?
For anyone working in DV. would you consider this good preparation for a verification career, or would a more conventional project (building a full UVM environment for a real IP, coverage closure, formal) serve me better?

I wrote this article a few years ago after an unsuccessful attempt at using XLS.

After XLS appeared in the recent OpenAI's Hotchips presentation, I thought I'd share this again.

In the second screenshot Rasavii says that a triode load consumes less voltage headroom because Vout max = Vdd while in a diode connected load Vout max equals Vdd-|Vthp|. We only get Vout max = Vdd in a triode load when we turn off M1, which turns off the current, which makes the resistance drop 0, so then Vdd is basically just Vout. I do not see the practical benefit of having Vout basically shorted to Vdd, because in my mind at least the diode connected load can achieve the specified headroom while the device can operate with some level of current. What am I missing?

I have a window to trial a change the documentation format for my company on our ASICs.

There are a bunch of basic needs. Hierarchy, moving from requirements to abstract function to design specs to implementations. Instructions for using blocks. Instances where a block is used and how. Registers.

Often, I've seen these things tracked in multiple design documents that get cluttered, repetitive, redundant, out of date... Not great. Plenty of issues from poor communication of expectations in how to use a block.

There are several things I am particular about. I want this to be readable by llms. I want this to be readable by people. I want this to be easy enough to edit and write (while I'm ok with having llm assistance in formatting, some people won't be). I want to have information exist in as few places as possible to avoid missing revisions and having contradictions. I want to be able to recall documentation relevant to previous chip revisions. I want to avoid licenses or deprecation. I want this to look nice. I would like this to be fast and interconnected.

There are several objects people use that make this just a hair more complex than "just use a markdown repo with templates." Timing diagrams, circuit schematics, data plots, block diagrams, math, variables, so many tables. I'm sure most people will want to stick with their preference and export images from their tools for all of these. It would be really nice if we could have text defined diagrams so we could diff documents and see specific changes instead of whole images, so I want to support that, but I don't expect buy-in.

I've found a few fancy markdown modifications on github. I built a demo of a block with MyST markdown and Sphinx which has let me do quite a bit of what I want, including little preambles in files to say what rev they apply to and yaml objects to hold requirements and such that documents can reference, but I've gotten hung up on timing diagrams and equations. I don't want to bark up the wrong tree for too long.

Obviously I can't share my demo since it is very much IP.

Some chip development failures I'm trying to avoid:

- the sensitivity on a sensor changes. Multiple documents refer to this function and specify the sensitivity or thresholds for different dac codes. Without knowing where every use of the sensitivity is, one has to read through every document and search with a broad vocabulary, and have multiple document owners change things. If the combined documentation had a defined variable for sensitivty everyone used, one change could be made, and the documents where that variable is used could be flagged for review.

- a 4 channel adc is treated as its own block despite being a sub block of many other blocks. Sampling is controlled by the requesting block. Most blocks use uniform time spacing for sampling the channels, but some do not. As these are separate functions, no document specifies all clock slots used for each adc. Conflicts emerge between blocks requesting measurements. The ADC owner assumes uniform sampling as they write test programs. Test programs fail, known immediately, and blocks don't work simultaneously, known only after someone tries that. Determining the reason requires crossing multiple documents to determine relative timings. An implementation table could send info back to the ADC documentation and have all relative timings shown in inplementations, and excerpts in relevant blocks.

Does anyone have experience trying this? Any tips? Anything you love or hate about your documentation? Recommended approaches? I don't think this is an absurd undertaking given the cost of chip revisions caused by bad documentation.

Looking to find out what the SE-TTIP group at Arm does

If anyone who has worked at Arm or partnered with this division knows what the TTIP acronym stands for and what their primary domain/responsibilities are?

Thanks!

Heard that Synopsys is laying off 40 Percent of its Workforce .One of the acquaintance I know personally is getting laid off . How's the Situation right now ?

I gave my managerial round of interview last week for Siemens EDA Noida for an entry level role. HR told me that my offer is kept on hold and they are interviewing other candidates too and if they don't find a better one than me, they will consider me.

The interview process has been done for 3 weeks. 6 people + manager, total 7 people interviewed me and each took at least an hour.

Can I consider this as rejection and move on? If not and if they are still considering me what should I ask in call to HR so that I can wait. I have an offer from another company but for comparatively less pay than siemens which have been delaying the joining for Siemens interview. So now I need to make the decision. Please suggest me in making decisions

Thank you

Hi everyone,

I'm an international first-year Master's student at Tampere University, currently pursuing a Master's in SoC Design. I'm planning to look for internships in Finland and would really appreciate some advice from people who have experience with the Finnish job market.

How do students usually find internships in this field? Are there any specific companies, job portals, networking strategies, or skills that you would recommend focusing on?

Any advice would be greatly appreciated. Thank you!

COM (Channel Operating Margin) is a standardized method for evaluating the performance margin of a high-speed SerDes channel At a high level, COM answers a simple but important question:

Given a particular channel, transmitter, receiver, equalization scheme, noise, and crosstalk environment, how much margin does the link have?

Instead of evaluating the channel only by its insertion loss or eye diagram, COM attempts to combine the major contributors to link performance into a single metric.This makes COM particularly useful for high-speed link design and signoff.

COM is a figure of merit for a channel derived from a measurement of its scattering parameters. It provides a quantitative measure of the overall channel operating margin by accounting for major link impairments, including channel loss, reflections and mismatch, ISI, crosstalk, noise, jitter, and the specified transmitter/receiver equalization. COM has become an important link-level metric for high-speed Ethernet interfaces, particularly as data rates continue to scale toward 224G/lane and beyond . COM is defined by Equation:

where As represents the signal amplitude and Ani represents the equivalent noise-and-interference amplitude at the specified detector error ratio

the figure above illustrates the reference model that is the basis for the calculation for COM. it can be viewed as a complete end-to-end SerDes link, including the transmitter, channel, package, crosstalk, receiver equalization, noise, and jitter.

The model starts with a randomly selected input symbol from an L-level alphabet (NRZ=2,PAM4=4). The transmitter generates the corresponding pulse with amplitude At and baud rate fb. The transmitter may include feed-forward equalization (FFE), represented by Hffe(f), which models the transmit-side equalization applied before the signal enters the physical channel.

The signal then passes through the transmitter package and channel under test. The channel is represented using S-parameter models. In the reference model, the victim path is divided into several sections, including the transmitter package, the on-board channel, and the receiver package. The reference points TP0 and TP5 define important locations for channel characterization and measurement.

In parallel with the victim channel, one or more aggressor channels are modeled to represent crosstalk. The aggressor transmitters generate independent signals, which propagate through their corresponding package and channel paths. The resulting crosstalk contribution is then coupled into the victim path.

At the receiver side, the received victim signal and the accumulated crosstalk contribution are combined. An additional input-referred noise term is added to represent receiver noise. The model also introduces jitter at the sampling stage, deterministic jitter (DJ) and random jitter (RJ),which will be disscussed in a future post

Finally, the resulting signal is processed by the receiver front-end, which includes the receiver response and CTLE, followed by a decision-feedback equalizer (DFE). The DFE attempts to recover the transmitted symbols, and the resulting detection errors are used to evaluate the link performance.

So, what does a “good” COM value look like? In many IEEE 802.3 Ethernet specifications, the minimum requirement is COM ≥ 3 dB. This means that even after accounting for the specified channel loss, ISI, crosstalk, noise, jitter, and equalization assumptions, the link should still maintain at least 3 dB of COM. The higher the COM value, the more margin the channel has against the modeled impairments.

END

Through this article, I hope you now have a better understanding of what COM is and how the COM reference model evaluates the overall performance margin of a high-speed SerDes link.From channel loss and ISI to crosstalk, noise, jitter, and equalization, COM provides a standardized way to bring these factors together into a single link-level metric.

If you find this article helpful, feel free to subscribe to this account.If you have any questions Let’s discuss, learn, and make progress together.

See you next time!

I want to understand how difficult this transition is and from long term perspective if its a good sensible move?