I'm 19, first year Electrical and Electronics Engineering in Turkey. I'm interested in computer architecture. I research on memory systems and DRAM security, I'm in a computer architecture lab at my university. The plan was a PhD abroad and then working somewhere that designs its own chips.

I've started doubting that plan and I want to hear from people who actually work in the field.

1. Placement and floorplanning seem mostly automated now (AlphaChip, Cerebrus, DSO.ai), and LLM generated RTL keeps improving. If you work in RTL, verification or architecture, has your actual day to day changed much in the last two years? Are teams hiring fewer juniors?
2. Is it true that architecture, spec and verification are the hardest parts to automate and physical design is the easiest? Or is that just what people want to believe?
3. Is it getting harder for new grads to get into hardware, like it clearly has in software? Is the engineer shortage everyone talks about real from the inside?
4. What actually counts for a hardware job or a PhD application? A working and verified core on an FPGA? Open source silicon contributions? Papers? I have 2-3 years and I want to spend them on the right thing.
5. I'm a Turkish citizen. How much do visas and export control/clearance rules actually block you in this field? Is Europe easier than the US for hardware?
6. How does pay grow for a hardware engineer over 10-15 years compared to software? Not exact numbers, just the shape of it.

Why I'm asking all this: here medicine is the default safe high income path, my exam score was good enough for it and I picked engineering instead. I'm reconsidering, and I'd rather decide based on real information. Honest answers are fine, I don't need to be encouraged.

Thanks.

Senior ASIC Verification Engineer

I am hiring for both ASIC Design and Verification Engineers - both Mid and Senior levels. These are all full time, direct hires with Cornelis Networks. Good salary and benefits with Series B Equity. Please email ( [scott.kwait@cornelisnetworks.com](mailto:scott.kwait@cornelisnetworks.com) ) me directly for consideration, direct applicants only (no agencies or 3rd parties). Apply directly using this link for the US, or this link for Costa Rica.

Job Description

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.  

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. 

Cornelis Networks is hiring a Senior ASIC Verification Engineer with advanced skills and knowledge in key areas required to verify world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. As a member of the ASIC leadership team with hands-on technical experience, you will be responsible for the verification closure of entire projects, including design modules, sub-systems, and SoCs. You will drive a wide range of activities including test-planning, UVM based testbench development, regression and coverage closure. You will have the opportunity to partner and collaborate with ASIC design, emulation, system hardware and post-silicon teams and help create a first-pass silicon success. A preferred candidate will have 8+ years of relevant experience in networking hardware verification, proven expertise in verifying one or more of the following: 50G, 100G, 400G Ethernet MAC/PCS protocols, UDP, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking. Experience utilizing AI tools to generate test plans and improve the productivity of verification process and team is highly desirable.

 Key Technical Responsibilities:

• Define overall SOC level verification strategy, technical planning, direction
• Enable and drive the development of UVM environments to verify RTL at block, unit, and SoC levels
• Develop and execute functional tests according to verification test plans
• Instrument TB for functional and code coverage and drive to closure based on the coverage metrics
• Collaborate with cross-functional teams like design, software, emulation and silicon validation teams towards ensuring the highest design quality

Team Responsibilities: 

• Day-to-day guidance and leadership of team members
• Driving results via mentoring, coaching, and counseling
• Education of team in the use of AI tools to enhance productivity and efficiencies
• Generation and enforcement of coding and verification guidelines

Minimum Qualifications: 

• 8+ years of experience with the following:
• Hands-on experience with writing code using UVM/System Verilog
• Verification for complex SoCs that include multiple clock and reset domains, using VCS or equivalent simulation tools
• Debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
• Experience in ground up testbench development
• Experience with revision control systems like Git or SVN etc.
• B.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering

Preferred Qualifications: 

• M.S. Degree in Computer Engineering, Computer Science, or Electrical Engineering
• 8+ years of relevant experience in networking hardware verification, proven expertise in verifying 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking
• One or more scripting languages (TCL, Python, Perl, Shell-scripting)
• Track record of first-pass success in ASIC and Systems

Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.  

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. 

In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. 

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. 

I am an analog designer working in memory phy ( ddr/lpddr/ gddr). Mostly in the receiver design. Getting a very lucrative offer but the team does IO designs ( GPIO, LVDS, I2C, I3C etc) and POR circuits. Should I jump the ship?

Given I have 7 yoe currently. I am thinking to chose new company and stay for 2-3 years and then move back to high speed. This compensation is extremely good that what’s making my mind swing.

Please guide what are pros and cons?

I wrote this article a few years ago after an unsuccessful attempt at using XLS.

After XLS appeared in the recent OpenAI's Hotchips presentation, I thought I'd share this again.

Hey everyone,

I’m currently pursuing my M.Tech and aiming to build a career in Physical Design.

So far, my hands-on exposure includes:

• Custom IC / Analog Design: CMOS circuit design and physical layout in Cadence Virtuoso, along with manual layout optimization (DRC/LVS/PEX).
• RTL-to-GDSII Implementation: Full digital implementation flow using both commercial suites (Cadence Innovus/Genus) and open-source EDA tools (OpenLane/OpenROAD).
• Synthesis & Timing Exploration: Experimented with dynamic frequency scaling during synthesis to analyze its impact on power, area, and timing metrics (WNS/TNS).

I want to take my practical understanding to the next level and work on something that closely mimics real-world industry challenges rather than just running a standard flow on a toy block.

For the PD engineers here:

1. What specific project would you recommend I work on next?
2. Which open-source blocks/macros or benchmark suites (like RISC-V cores, OpenPOWER, or complex DSP blocks) are best suited for demonstrating solid PD skills?
3. What specific tapeout-ready skills or edge cases do hiring managers look for on a fresh grad’s resume that set them apart?

Any feedback, project ideas, or resources would be greatly appreciated! Thanks in advance.

Hello everyone,

I am an electronics and electrical communication engineering fresh grade and I have a very bad GPA 2/4

but I have taped out an edge ai chip for my graduation project and it was sponsored by a small design house on some old node and fortunately this chip went commercial. I also have 2 ieee publications ( the 2 papers are related to my graduation project). I need to apply to a master at one of top tier universities specially in Europe to make up the bad bachelor records but I think I won't be accepted due to this GPA. any recommendations or advices ?

It doesn't have to be sponsored, I can self fund my master

Final year ECE student. I’m doing an internship at a semiconductor company right now with the DV team, and they’ve offered to host my final year project. The title they proposed is about using LLMs for design verification.
I’m targeting front-end ASIC roles after graduation DV and RTL design, I’m open to either. So my concern is this: will a project like this actually give me a solid understanding of verification UVM, coverage, assertions, debugand. And enough design-side depth to be credible for RTL roles too or will I spend the whole year on prompting, scripting, and pipeline plumbing and come out knowing more about LLMs that about hardware?
For anyone working in DV. would you consider this good preparation for a verification career, or would a more conventional project (building a full UVM environment for a real IP, coverage closure, formal) serve me better?